In my collage, me and my team (AIExtreme) was asked to develop risc processor 32-bit pipelined with assembler. In this post i will demonstrate the latest work in the processor and show the project development phases and status.

Processor Features:

1. Processor Support 48 Instruction up to 256 Instruction
2. Processor Interface with 2 Memories [16bit Address, 16bit Data] Interleaved
3. Interface with LCD Terminal using Instructions
4. Processor have it’s Assembler

The Processor Development Phases

1. Conceptual Design and Simulation [Completed]
2. Implementation [Not Started Yet]

Conceptual Design and Simulation

Processor Stages

Processor Architecture

Processor in Simulation

Processor Assembler Developed By C#

Instruction Set:

1. Immediate Mode
2. Register Mode
3. Direct Addressing Mode
4. Indirect Addressing Mode

Scheme: Opcode – Description

00-NOP
01-MOV reg,immediate
02-ADD d.reg,s1.reg,s2.reg
03-ADC d.reg,s1.reg,s2.reg
04-SUB d.reg,s1.reg,s2.reg
05-SUW d.reg,s1.reg,s2.reg
06-MUL d.reg,s1.reg,s2.reg
07-DIV d.reg,s1.reg,s2.reg
08-TRSA d.reg,s1.reg
09-TRSB d.reg,s2.reg
0a-AND d.reg,s1.reg,s2.reg
0b-OR d.reg,s1.reg,s2.reg
0c-NAND d.reg,s1.reg,s2.reg
0d-NOR d.reg,s1.reg,s2.reg
0e-XOR d.reg,s1.reg,s2.reg
0f-XNOR d.reg,s1.reg,s2.reg
10-NOT d.reg,s1.reg
11-CMP reg1,reg2
12-IPNT immediate
13-RPNT reg
14-DSTOWE address,reg
15-DSTOWO address,reg
16-DSTODW address,reg
17-DLODWE reg,address
18-DLODWO reg,address
19-DLODDW reg,address
1a-JG address
1b-JE address
1c-JL address
1d-JC address
1e-JNG address
1f-JNE address
20-JNL address
21-JNC address
22-JMP address
23-IDSTOWE address
24-IDSTOWO address
25-IDSTODW address
26-IDLODWE address
27-IDLODWO address
28-IDLODDW address
29-PUSHWE reg
2a-PUSHWO reg
2b-PUSHDW reg
2c-POPWE reg
2d-POPWO reg
2e-POPDW reg
2f-INC reg,immediate
30-DEC reg,immediate

Future Work

1. Develop C Compiler For The Processor
2. Implementing it On FPGA
3. Improve The Processor with More Features & Instructions

The Processor Circuit and Assembler is Now Available on Google Code.

Next Processor Projects: Developing CISC Processor, isA